Improvement of column-parallel sampling for a monolithic pixel detector

Monolithic pixel detectors often use an on-chip analog to digital converter (ADC) with successive approximation register (SAR) to digitize the signal amplitude of the pixels. This paper solves the challenges of column-parallel sampling with respect to the layout, power consumption, process variability, speed, and the integration of fully differential ADC architecture with ADC driver. To save power and area, a single column ADC digitizes the signals from two columns. A fully differential amplifier (ADC driver) is used to convert a single-ended signal from a pixel to the differential signal for driving the fully differential SAR ADC inputs. An implemented prototype occupies 445 × 115 μ m² and achieves 4 MHz sampling frequency. The overall power consumption is 200 μ W from a 1.8 V power supply at 10 frames per second readout frequency.