Analysis of admittance measurements of MOS capacitors on CVD grown bilayer MoS2
Abstract
In this study we present results on the AC admittance response of bilayer MoS2 films grown using chemical vapor deposition. A new MOS capacitor design for ultra-thin body 2D materials is proposed. We show that along with the density of interface traps (Dit), a transverse electric field distribution in the semiconductor and parasitic capacitance also cause frequency dispersion in measured capacitance. Dit extracted using the conductance method in 40 devices indicates reliable measurements for channel length, L < 10 [ image ]m. For devices with L > 10 [ image ]m, an increase in Dit is an artifact of access resistance in the semiconductor. Temperature measurements show an increasing defect distribution from [ image ] cm-2 eV-1 around mid-gap to [ image ] cm-2 eV-1 close to the conduction band minimum.
- Publication:
-
2D Materials
- Pub Date:
- July 2019
- DOI:
- 10.1088/2053-1583/ab20fb
- Bibcode:
- 2019TDM.....6c5035G
- Keywords:
-
- 2D materials;
- MX2;
- admittance;
- capacitance;
- interface traps;
- MoS2;
- 2D MOS capacitor