A parallel timing synchronization architecture for all-digital coherent receiver

Timing synchronization is critical in digital demodulation systems such as intradyne optical receivers. In this paper, a novel timing recovery method for all-digital coherent receivers is proposed. With the help of a parallel architecture, the new method can be implemented on ASIC or FPGA platform, especially when the symbol rate is much higher than the clock rate of FPGAs. Through adjusting the frame structure in the parallel interpolator, the receiver synchronizes its symbol rate with the transmitter. Different from existing parallel timing recovery methods, the proposed method does not adjust the period between adjacent frames of samples, which can be beneficial to the subsequent processing in hardware. The performance is tested by simulation in QPSK modulation. Under relative clock offset between +/-50 ppm and jitter noise with 0.3% standard deviation, the proposed method shows almost no degradation compared with its serial equivalent. Combined with different timing error detection algorithms, this method can be used in kinds of modulation formats like MPSK and QAM.