High-Accuracy and Fault Tolerant Stochastic Inner Product Design
Abstract
In this work, we present a novel inner product design for stochastic computing. Stochastic computing is an emerging computing technique, that encodes a number in the probability of observing a one in a random bit stream. This leads to reduced hardware costs and high error tolerance. The proposed inner product design is based on a two-line bipolar encoding format and applies sequential processing of the input in a central accumulation unit. Sequential processing significantly increases the computation accuracy, since it allows for preliminary cancelation of carry bits. Moreover, the central accumulation unit gives a much better scalability compared to conventional adder tree approaches. We show that the proposed inner product design outperforms state-of-the-art designs in terms of hardware costs for high accuracy requirements and fault tolerance.
- Publication:
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arXiv e-prints
- Pub Date:
- August 2018
- DOI:
- 10.48550/arXiv.1808.06500
- arXiv:
- arXiv:1808.06500
- Bibcode:
- 2018arXiv180806500H
- Keywords:
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- Computer Science - Emerging Technologies;
- Electrical Engineering and Systems Science - Signal Processing
- E-Print:
- This paper has been submitted to IEEE Transactions on Circuits and Systems II: Express Briefs