Gate voltage dependent 1/f noise variance model based on physical noise generation mechanisms in n-channel metal-oxide-semiconductor field-effect transistors
Abstract
1/f noise is one of the most important characteristics for designing analog/RF circuits including operational amplifiers and oscillators. We have analyzed and developed a novel 1/f noise model in the strong inversion, saturation, and sub-threshold regions based on SPICE2 type model used in any public metal-oxide-semiconductor field-effect transistor (MOSFET) models developed by the University of California, Berkeley. Our model contains two noise generation mechanisms that are mobility and interface trap number fluctuations. Noise variability dependent on gate voltage is also newly implemented in our model. The proposed model has been implemented in BSIM4 model of a SPICE3 compatible circuit simulator. Parameters of the proposed model are extracted with 1/f noise measurements for simulation verifications. The simulation results show excellent agreements between measurement and simulations.
- Publication:
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Japanese Journal of Applied Physics
- Pub Date:
- April 2015
- DOI:
- 10.7567/JJAP.54.04DC10
- Bibcode:
- 2015JaJAP..54dDC10A