ESD robustness concern and optimization for high-voltage p-type LDMOS transistor with thin gate oxide used as the output driver
The p-type lateral double-diffused MOS (pLDMOS) transistor with thin gate oxide has significant advantages when being used as a high side output driver in high-voltage ICs (HVICs), because it usually possesses larger current density compared with a device with thick gate oxide. However, in order to reduce the chip size, many HVICs do not have specialized output electrostatic discharge (ESD) protection cells, so the pLDMOS device is operated both as the output driver and the ESD protection structure. In this work, we have found that the ESD robustness of the pLDMOS with thin gate oxide is poor. As a result, this device is risky for those area-efficient HVICs. To solve the contradiction, the inner mechanism of the poor ESD robustness for the pLDMOS with thin gate oxide has been investigated. Moreover, an improved method, by adjusting the overlap length between the special p-well and the source p+ implantation region, has been presented. The experimental results show that the ESD robustness of the improved pLDMOS with thin gate oxide has been obviously increased, while the large current density can be also maintained.