A prototype hybrid pixel detector ASIC for the CLIC experiment
Abstract
A prototype hybrid pixel detector ASIC specifically designed to the requirements of the vertex detector for CLIC is described and first electrical measurements are presented. The chip has been designed using a commercial 65 nm CMOS technology and comprises a matrix of 64 × 64 square pixels with 25 μm pitch. The main features include simultaneous 4-bit measurement of Time-over-Threshold (ToT) and Time-of-Arrival (ToA) with 10 ns accuracy, on-chip data compression and power pulsing capability.
- Publication:
-
Journal of Instrumentation
- Pub Date:
- January 2014
- DOI:
- 10.1088/1748-0221/9/01/C01012
- Bibcode:
- 2014JInst...9C1012V