Effect of electrical stress on Au/Pb (Zr0.52Ti0.48) O3/TiOxNy/Si gate stack for reliability analysis of ferroelectric field effect transistors

Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure with 20 nm thin lead zirconate titanate (PZT) ferroelectric film and 6 nm ultrathin high-κ titanium oxynitride (TiO_xN_y) insulator layer on p-Si substrate were fabricated. Effect of constant voltage stress (CVS) on electrical characteristics of MFIS structure was investigated to study the reliability of fabricated devices. The experimental results showed trivial variation in memory window (ΔW) from 1.05 to 1 V under CVS of 0 to 15 V (5.76 MV/cm) at sweep voltage of ±5 V. Also, leakage current density (J) reduced from 5.57 to 1.94 μA/cm² under CVS of 5.76 MV/cm, supported by energy band diagram. It signifies highly reliable TiO_xN_y buffer layer for Ferroelectric Random Access Memory. After programming at ±5 V, the high (C_H) and low (C_L) capacitances reliability remains distinguishable for 5000 s even if we extrapolate measured data to 15 years. Microstructures analysis of XRD reveals the formation of (100) and (111) orientation of PZT and TiO_xN_y, respectively. Thus, Au/PZT/TiO_xN_y/Si, MFIS gate stacks can be potential candidate for next generation reliable Ferroelectric Field Effect Transistors.