Process Engineering and Trap Distribution for Dielectric/Si Interfacial Layer in High-k Gated MOS Devices Chang-Liao, Kuei-Shu ; Fu, Chung-Hao ; Lu, Chun-Chang ; Chang, Yu-An ; Hsu, Ya-Yin ; Tsao, Che-Hao ; Wang, Tien-Ko ; Heh, Da-Wei ; Li, Y. C. ; Tsai, Wen-Fa ; Ai, Chi-Fong ; Hou, Fu-Chung ; Hsu, Yao-Tung Abstract Publication: ECS Transactions Pub Date: April 2011 DOI: 10.1149/1.3572274 Bibcode: 2011ECSTr..35d..39C