Advanced patterning studies using shaped e-beam lithography for 65-nm CMOS preproduction

With the objective to ramp-up 65 nm CMOS production in early 2005, preliminary works have to start today to develop the basic technological in order to be correctly prepared. In the absence of commercial advanced 193 nm scanners compatible with these aggressive design rules, electron beam technology was employed for the realization of a first 6-T SRAM cell of a size of 0.69 μm². This paper highlights the work performed to integrate E-beam lithography in this first 65 nm CMOS process flow.