Scaling of MOSFETs for future technology generations: Circuit and device scaling, front end processing issues, and advanced MOSFET structures
Abstract
The development of advanced MOSFETs for future IC technology generations is discussed, starting from circuit and MOSFET scaling trends and requirements. Front end processing issues and potential solutions such as high-k gate dielectric, metal gate electrode, etc., are discussed as well. Finally, the issues with scaling classical planar bulk CMOS transistors into the deep sub-100nm regime and the potential of advanced structures such as strained silicon, SOI, and double gate MOSFETs in this regime are considered. The perspective is from the 2001 International Technology Roadmap for Semiconductors (ITRS).
- Publication:
-
APS March Meeting Abstracts
- Pub Date:
- March 2003
- Bibcode:
- 2003APS..MAR.G3002Z