Development of a pixel readout chip for BTeV
Abstract
A description is given of the R&D program underway at Fermilab to develop a pixel readout ASIC appropriate for use at the Tevatron collider. Results are presented from tests performed on the first prototype pixel readout chip designed at Fermilab, and a new readout architecture is described.
- Publication:
-
Nuclear Instruments and Methods in Physics Research A
- Pub Date:
- October 1999
- DOI:
- 10.1016/S0168-9002(99)00421-0
- Bibcode:
- 1999NIMPA.435..144C