Timing and area optimization for VLSI circuit and layout
Abstract
This thesis considers two problems in computeraided design of VLSI circuits: (1) discrete gate sizing and (2) timingdriven placement improvement. The discrete gatesizing problem is described as follows. A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After presenting an efficient solution algorithm for combinational circuits, we examine the problem of minimizing the area of a synchronous sequential circuit for a given clock period specification. This is done by appropriately selecting a size for each gate in the circuit and by adjusting the delays between the central clock distribution node and individual flipflops. Existing methods treat these two problems separately, which may lead to very suboptimal solutions in some cases. We develop a novel unified approach to tackle them simultaneously. We also address the problem of making this work applicable to very large synchronous sequential circuits by partitioning these circuits to reduce the computational complexity.
 Publication:

NASA STI/Recon Technical Report N
 Pub Date:
 May 1994
 Bibcode:
 1994STIN...9516089C
 Keywords:

 Computer Aided Design;
 Computer Design;
 Layouts;
 Linear Programming;
 Logic Design;
 Very Large Scale Integration;
 Algorithms;
 FlipFlops;
 Gates (Circuits);
 Logic Circuits;
 Electronics and Electrical Engineering