A verification logic representation of indeterministic signal states
Abstract
The integration of modern CAD tools with formal verification environments require translation from hardware description language to verification logic. A signal representation including both unknown state and a degree of strength indeterminacy is essential for the correct modeling of many VLSI circuit designs. A higher-order logic theory of indeterministic logic signals is presented.
- Publication:
-
3rd NASA Symposium on VLSI Design
- Pub Date:
- 1991
- Bibcode:
- 1991vlsi.sympR....G
- Keywords:
-
- Logic Design;
- Logic Programming;
- Program Verification (Computers);
- Signal Processing;
- Very Large Scale Integration;
- Computer Aided Design;
- Logic Circuits;
- Machine Translation;
- Memory (Computers);
- Software Tools;
- Electronics and Electrical Engineering