Analysis of CMOS-compatible lateral insulated base transistors

Performance results are reported for various lateral insulated-base transistors (LIBTs) fabricated with a 2.5-micron digital CMOS-compatible high-voltage integrated circuit (HVIC) process. Structural modifications have been proposed to the LIBTs reported to date, in order to improve their on-stage performance. The modifications have been achieved with the use of charge-controlled n(+) buried layers incorporated within the device structures. The fabrication process utilizes three additional steps carried out prior to the CMOS fabrication sequence. An important feature of this HVIC process is the use of a 40-nm gate oxide, which makes the power devices fully compatible with the low-voltage digital circuits. During this work, a specific on-resistance of 0.016 ohm sq cm and a turn-off delay of 90 nsec have been obtained in an improved LIBT structure which is capable of withstanding up to 250 V.