A systematic approach for design of digitserial signal processing architectures
Abstract
A systematic unfolding transformation technique for transforming bitserial architectures into equivalent digitserial ones is presented. The novel feature of the unfolding technique lies in the generation of functionally correct control circuits in the digitserial architectures. For some applications bitserial architectures may be too slow, and bitparallel architectures may be faster than necessary and may require too much hardware. The desired sample rate in these applications can be achieved using the digitserial approach, where multiple bits of a sample are processed in a single clock cycle. The number of bits processed in one clock cycle in the digitserial systems is referred to as the digit size; the digit size can be any arbitrary integer (the digit size was restricted to be a divisor of wordlength in past ad hoc designs). Digitserial implementation of two's complement adders and multipliers is described. Leastsignificantbitfirst bitserial implementation of two's complement division, squareroot, and compareselect operations are presented, and the corresponding digitserial architectures for these operations are obtained using the unfolding algorithm. Unfolding of multiplerate operations (such as interpolators and decimators) is also addressed.
 Publication:

IEEE Transactions on Circuits Systems
 Pub Date:
 April 1991
 Bibcode:
 1991ITCS...38..358P
 Keywords:

 Architecture (Computers);
 Bit Synchronization;
 Computer Systems Design;
 Logic Circuits;
 Signal Processing;
 Bit Error Rate;
 Digital Techniques;
 Parallel Processing (Computers);
 Transformations (Mathematics);
 Electronics and Electrical Engineering