A 45-ns 64-Mb DRAM with a merged match-line test architecture Mori, S. ; Miyamoto, H. ; Morooka, Y. ; Kikuda, S. ; Suwa, M. ; Kinoshita, M. ; Hachisuka, M. ; Arima, H. ; Yamada, M. ; Yoshihara, T. ; Kayano, S. Abstract Publication: IEEE Journal of Solid-State Circuits Pub Date: November 1991 DOI: 10.1109/4.98962 Bibcode: 1991IJSSC..26.1486M