Coherence and satisfiability of waveform timing specifications

Hardware designers often use digital waveforms to specify critical device timing. Several problems related to the use of such specifications are analyzed. These include the verification of the coherence of specifications; the determination of whether each device's timing requirements are satisfied by the timing of other devices in the system, given the timing specifications of devices in a system; and derivation of the conditions that must be met for the timing of a system to be considered reliable, when specifications are incomplete. Timing specifications are formulated as sets of linear constraints, and it is shown that the problems can be solved with optimization techniques. Several algorithms are presented along with open problems concerning efficient solutions. In addition, a model is proposed for the propagation of events in a digital circuit that can serve as a basis for the timing bounds found in specifications. This model is used to show that the method used to test the satisfiability of specifications is safe in the sense that affirmative answers are trustworthy while negative answers may be conservative. The work reported can serve as a basis for the design of computer aided design tools for validating timing specifications, analyzing the timing of device connections, and synthesizing the conditions that ensure reliability.