The organization of permutation architectures with bussed interconnections
Abstract
The problem of efficiently permuting data stored in VLSI chips is explored in accordance with a predetermined set of permutations. By connecting chips with shared bus interconnections, as opposed to point-to-point interconnections, it is shown that the number of pins per chip can often be reduced. Uniform permutation architectures were also considered that realize permutations in several clock ticks, instead of one, and show that further savings in the number of pins per chip can be obtained.
- Publication:
-
NASA STI/Recon Technical Report N
- Pub Date:
- January 1989
- Bibcode:
- 1989STIN...9010352K
- Keywords:
-
- Architecture (Computers);
- Chips (Electronics);
- Group Theory;
- Joining;
- Permutations;
- Very Large Scale Integration;
- Clocks;
- Electric Connectors;
- Pins;
- Electronics and Electrical Engineering