Fault tolerant VLSI (Very Large-Scale Integration) design using error correcting codes
Abstract
Very Large-Scale Integration (VLSI) provides the opportunity to design fault tolerant, self-checking circuits with on-chip, concurrent error correction. This study determines the applicability of a variety of error-detecting, error-correcting codes (EDAC) in high speed digital data processors and buses. In considering both microcircuit faults and bus faults, some of the codes examined are: Berger, repetition, parity, residue, and Modified Reflected Binary codes. The report describes the improvement in fault tolerance obtained as a result of implementing these EDAC schemes and the associated penalties in circuit area.
- Publication:
-
NASA STI/Recon Technical Report N
- Pub Date:
- February 1989
- Bibcode:
- 1989STIN...8927096H
- Keywords:
-
- Chips (Electronics);
- Computer Programs;
- Error Correcting Codes;
- Error Detection Codes;
- Fault Tolerance;
- Very Large Scale Integration;
- Automatic Control;
- Binary Codes;
- Checkout;
- Errors;
- Large Scale Integration;
- Microelectronics;
- Parity;
- Reflection;
- Electronics and Electrical Engineering