Pressure Sensitive Insulated Gate Field Effect Transistor
A pressure sensitive insulated gate field effect transistor has been developed. The device is an elevated gate field-effect-transistor. It consists of a p-type silicon substrate in which two n^+ region, the source and drain, are formed. The gate electrode is a metal film sandwiched in an insulated micro-diaphragm resembling a pill-box which covers the gate oxide, drain, and source. The space between the gate electrode and the oxide is vacuum or an air-gap. When pressure is applied on the diaphragm it deflects and causes a change in the gate capacitance, and thus modulates the conductance of the channel between source and drain. A general theory dealing with the characteristic of this pressure sensitive insulated gate field effect transistor has been derived, and the device fabricated. The fabrication process utilizes the standard integrated circuit fabrication method. It features a batch fabrication of field effect devices followed by the batch fabrication of the deposited diaphragm on top of each field effect device. The keys steps of the diaphragm fabrication are the formation of spacer layer, formation of the diaphragm layer, and the subsequent removal of the spacer layer. The chip size of the device is 600 μm x 1050 mum. The diaphragm size is 200 μm x 200 mum. Characterization of the device has been performed. The current-voltage characteristics with pressure as parameters have been demonstrated and the current-pressure transfer curves obtained. They show non-linear characteristics as those of conventional capacitive pressure sensors. The linearity of threshold voltage versus pressure transfer curves has been demonstrated. The temperature effect on the device performances has been tested. The temperature coefficient of threshold voltage, rather than the electron mobility, has dominated the temperature coefficient of the device. Two temperature compensation schemes have been tested: one method is by connecting two identical PSIGFET in a differential amplifier configuration, and the other is by tying the gate to drain and flowing with an optimum drain current. The noise generated by the device has been recorded; and the frequency response has been tested.
- Pub Date:
- Physics: Electricity and Magnetism