Curing dynamics of a glass-fiber cylinder on electron beam irradiation
Abstract
A testable CMOS design technique in which some extra transistors are used in such a way that the CMOS gate is converted to a pseudo-nMOS/pMOS gate during testing is discussed. With the proposed design technique, CMOS open faults can be detected regardless of timing skews/delays, glitches, or charge sharing among the internal nodes. The major advantage of the proposed testable design technique is that it allows the use of a single test vector to detect a stuck-open fault. This significantly reduces the complexity of test generation and the time consumed for testing. The design procedure is simple and all the classical algorithms and automatic test-pattern-generating programs can be used to generate tests for circuits designed according to this technique. Even random testing techniques can be used efficiently to detect the open faults in these CMOS circuits.
- Publication:
-
IEEE Journal of Solid-State Circuits
- Pub Date:
- August 1989
- DOI:
- 10.1007/BF00616274
- Bibcode:
- 1989IJSSC..24.1055R
- Keywords:
-
- Cmos;
- Electronic Equipment Tests;
- Fault Tolerance;
- Field Effect Transistors;
- Logic Circuits;
- Test Pattern Generators;
- N-Type Semiconductors;
- Nondestructive Tests;
- P-Type Semiconductors;
- Robustness (Mathematics);
- Electronics and Electrical Engineering