A network architecture for radar signal processing

This paper presents design goals, an architecture, and simulation results for a new generation of programmable radar signal processors. The design goals for future processors include increased programmability, performance, reliability, and availability. A new network architecture for interprocessor communication is introduced to meet these design goals. The network is optimal in that it provides the maximum number of processors and memories with single-path unit-delay interconnection. Advanced simulation tools have been used to evaluate the performance and reliability of the new interconnection architecture. The architecture is shown to be efficient for typical radar signal processing tasks.