A 40-ps high electron mobility transistor 4.1K gate array
Abstract
A high-electron mobility transistor (HEMT) 4.1K-gate array has been developed, using a selective dry etching process and a MBE (molecular-beam epitaxy) growth technology. The circuit design uses direct-coupled FET logic (DCFL). The chip contains 4096 NOR gates, each with a 0.8-micron gate length, and measures 6.3 mm x 4.8 mm. A basic gate delay of 40 ps has been achieved. A 16 x 16-bit parallel multiplier, used to test this array, has a multiplication time of 4.1 ns at 300 K, where the power dissipation is 6.2 W.
- Publication:
-
IEEE Journal of Solid-State Circuits
- Pub Date:
- April 1988
- DOI:
- 10.1109/4.1011
- Bibcode:
- 1988IJSSC..23..485K
- Keywords:
-
- Chips (Electronics);
- Etching;
- Gates (Circuits);
- High Electron Mobility Transistors;
- Molecular Beam Epitaxy;
- Aluminum Gallium Arsenides;
- Arrays;
- Equivalent Circuits;
- Large Scale Integration;
- Multipliers;
- Parallel Processing (Computers);
- Electronics and Electrical Engineering