64 Mb bubble memory chip architecture
Abstract
The present 64-Mb bubble memory chip architecture uses ion-implanted tracks and a dual gate with block replicate and swap functions to form 16 4-Mb blocks; these have 1160 minor loops, with 4097-bit storage. A chip carrier with matrix diodes is connected to the memory chip in order to reduce the memory module's pin number. A novel matrix connection pulse-drive method is proposed which drives the 16 blocks in parallel, on the basis of a small number of drive circuits.
- Publication:
-
IEEE Transactions on Magnetics
- Pub Date:
- September 1987
- DOI:
- 10.1109/TMAG.1987.1065371
- Bibcode:
- 1987ITM....23.2572T
- Keywords:
-
- Bubble Memory Devices;
- Chips (Electronics);
- Ion Implantation;
- Diodes;
- Pulse Generators;
- Electronics and Electrical Engineering