A high-speed HEMT 1.5K gate array

A 1.5K-gate HEMT (high electron mobility transfer) gate array has been developed, using a direct-coupled FET logic circuit. The chip, containing 1520 basic cells and 72 I/O cells, was 5.5 mm x 5.6 mm. The basic circuit was designed for two different threshold voltages for D-HEMT, in order to obtain high-speed performance both at room and low temperatures. Fully functional 8 x 8-bit parallel multipliers were fabricated on the gate-array chip. At room temperature, a multiplication time of 3.7 ns, including I/O buffer delay, was achieved with a power dissipation of 6.0 W at a supply voltage of 1.6 V; at liquid-nitrogen temperature, multiplication time was 3.1 ns at a supply voltage of 0.95 V and the power dissipation of 3.2 W.