A low-power high-speed ion-implanted JFET for InP-based monolithic optoelectronic IC's
Abstract
A high-performance, fully ion-implanted planar InP junction FET fabricated by a shallow (4000-A) n-channel implant, an n(+) source-drain implant to reduce FET series resistance, and a p-gate implant to form a shallow (2000-A) abrupt p-n junction, followed by a rapid thermal activation, is described. From FET's with gates 2 microns long, a transconductance of 50 mS/mm, and an output impedance of 400 Ohm mm are measured at zero gate bias with a gate capacitance of 1.2 pF/mm. The FET has a threshold voltage of -2.4 V, and a saturated drain current of 60 mA/mm at V(gs) = 0 V with negligible drift.
- Publication:
-
IEEE Electron Device Letters
- Pub Date:
- November 1987
- DOI:
- 10.1109/EDL.1987.26714
- Bibcode:
- 1987IEDL....8..518K
- Keywords:
-
- Electrical Properties;
- Electro-Optics;
- Indium Phosphides;
- Integrated Circuits;
- Ion Implantation;
- Jfet;
- Capacitance;
- Carrier Density (Solid State);
- Electrical Impedance;
- P-N Junctions;
- Transconductance;
- Volt-Ampere Characteristics;
- Electronics and Electrical Engineering