Very thin VLSIlayouts (Very Large Scale IntegrationLayouts) of complete binary trees
Abstract
Described is a minimum area VLSIlayout of a complete binary tree T sub k with all (2 sup k) leaves on one edge of a rectangular chip. The layout has the following additional properties: (1) there are no wirecrossings; (2) the root of the tree is accessible; and (3) it has minimum possible width. It is shown that any minimum area VLSIlayout of T sub k, with all leaves collinear must have width (k/2) + 1 and length (2 sup k) + 2 sup((k/2)  1) for k even and (2 sup k) + 2 sup ((k/2)1)(1 + (k/2)) for k odd.
 Publication:

Unknown
 Pub Date:
 June 1986
 Bibcode:
 1986vlsi.rept.....V
 Keywords:

 Binary Integration;
 Layouts;
 Thin Films;
 Trees (Mathematics);
 Very Large Scale Integration;
 Chips (Electronics);
 Circuit Diagrams;
 SolidState Physics