Evaluation and implementation of testability schemes for gate array integrated circuit design

The research undertaken involved efforts on two distinct testing problems associated with large-scale (LSI) and very-large-scale (VLSI) integrated circuits. One problem concerns the debugging of chip test set-ups, a chip that generates a unique identifying signal on each of its pads could be useful. Such a chip could drive each wiring connection which could then be sampled. The design, realization, and characteristics of such a tester chip are discussed. Also, several design for testability schemes for chips are summarized and their potential for use in gate array design procedures is discussed.