A high performance chip set implementation of a finite impulse response filter

The systolic properties of digital signal processing algorithms can most easily be exploited by specialized processors with simple architectures providing considerable parallelism and freedom from bottlenecks in the control and flow of data. The realization of such processors is facilitated by the availability of advanced IC process technologies, coupled with Computer Aided Design (CAD) techniques. A design example for a Finite Impulse Response (FIR) filter is presented. It consists of a small chip set; a multiplier-accumulator, a coefficient memory (consisting of Read Only Memory (ROM) or Random Access Memory (RAM) devices) and a Data Memory/Control Unit (DMCU). The latter, implemented with standard cell techniques, includes a 128 word x 16-bit data memory, generates all system control signals from a few simple external signals, and provides a simple asynchronous interface. The basis design concept is well suited for implementation using advanced technologies. Sub-micron silicon technology would provide improved performance and facilitate a single chip implementation, while gallium arsenide technology offers potential for real-time video signal processing. y would provide improved performance and facilitate a single chip implementation, while gallium arsenide technology offers potential for real-time video signal processing.