Increase of the packaging density of Very Large Scale Integration (VLSI) circuits using automatic alignment
Abstract
Experiments in a production line were conducted to investigate the possible reduction of safety distances in VLSI circuits when an automatic alignment system is used. The test setup is described. With the very accurate alignment system of the Philips silicon repeater, the safety distance between a contact hole and a polysilicon-gate in a modified microcomputer circuit is reduced 0.7 micron without any yield loss. Design rules based on these experiments, and on lithography investigations were applied to redesign a 4 k static read-only memory. The area of a single memory cell in this redesign is 825 59 microns, compared to 1800 sq microns in the original version, and the final chip area is reduced to 8 sq mm compared to 13 sq mm.
- Publication:
-
NASA STI/Recon Technical Report N
- Pub Date:
- March 1985
- Bibcode:
- 1985STIN...8610451F
- Keywords:
-
- Electronic Packaging;
- Printed Circuits;
- Self Alignment;
- Very Large Scale Integration;
- Design Analysis;
- Microcomputers;
- Photolithography;
- Product Development;
- Read-Only Memory Devices;
- Yield;
- Electronics and Electrical Engineering