Performance limits of scaled CMOS analog ICs
Abstract
A new concept of merging semi-custom CMOS analog circuits with the basic digital gate array approach is introduced with a 2 micron analog/digital gate array chip. Tradeoffs in the analog circuit performance using scaled digital CMOS technology were evaluated. Speed and precision performance limits in scaled CMOS analog integrated circuits based on pass transistor induced errors are investigated. Conventional single lump SPICE models used to analyze transients of MOS transistors assume quasi-static operation, which can easily be violated for high speed analog applications. New distributed and two lump models were created to analyze pass transistor turn-off transients for very short clock fall times. These models can be used to explain performance of transistors in the diffusion mode of operation. A pass transistor test chip including four kinds of new selectively doped pass transistors was designed, fabricated, and tested to verify the transient analysis. Measured transients are consistent with the model results.
- Publication:
-
Ph.D. Thesis
- Pub Date:
- 1985
- Bibcode:
- 1985PhDT........33K
- Keywords:
-
- Cmos;
- Doped Crystals;
- Errors;
- Integrated Circuits;
- Transistors;
- Analog To Digital Converters;
- Chips (Electronics);
- Gates (Circuits);
- Electronics and Electrical Engineering