C-band device depicts FET design techniques
Abstract
Three basic factors were considered in the design of an internally matched power FET, GaAs MESFET: (1) increase of total gate width (GW); (2) reduction of gate length (GL), source inductance (SI), and parasitic (P) elements; and (3) a high drain-to-source breakdown voltage (BDV). To increase the GW, which is proportional to the output power, the GW per finger was increased to 200 microns, thus reducing the chip size for a given total GW. Reduction of GL to 0.5 micron helped to achieve high gain through increased transconductance and decreased gate-to-source capacitance. Use of an airbridge, instead of a dielectric crossover, reduced P capacitance, while small drain and gate pads minimized the input and output P effects. The via-hole technique was employed to reduce the source SI and thermal resistance while increasing the thickness of the active epitaxial layer under the drain contact region helped to achieve high BDV. The described FET design provides good gain and up to 2-W output power at 8 GHz. Description and schematics of the airbridge and circuit microwave design are included.
- Publication:
-
Microwaves
- Pub Date:
- November 1985
- Bibcode:
- 1985MicWa..24...73H
- Keywords:
-
- Amplifier Design;
- C Band;
- Field Effect Transistors;
- Gates (Circuits);
- Network Synthesis;
- Computer Aided Design;
- Design Analysis;
- Direct Current;
- Gallium Arsenides;
- Radio Frequencies;
- Electronics and Electrical Engineering