Charge collection in CMOS/SOS structures

Charge collection measurements have been carried out in order to study the susceptibility of CMOS/SOS FET structures to charge funneling. The measurements were performed on FET designs having gate widths of 100 micrometers and varying gate lengths of 1.2-20 micrometers. A charge sensitive preamplifier having an integration time of 0.5 microseconds was used to measure the absolute charge collection efficiency, which is the ratio of the charge collected on a node of the test structure to the charge collected in a 100-percent-efficient surface barrier detector. The time dependence of the voltage pulse appearing on the FET node due to an ion strike was measured using a transient digitizer system. It is found that the fraction of the charge collected at individual nodes on the FETs was approximately equal to the amount of charge deposited on the silicon insulating layer, i.e., no charge collection took place in the insulating substrate. The stopping powers of CMOS/SOS FETs for ions entering the sapphire substrate are given in a table. It is shown that the ionizing power value of Cu ions, the most heavily ionizing ions observed was greater than that for the 2.5 MeV He ions by a factor of about 26.