Hi-MNOS II technology for a 64-kbit byte-erasable 5-V-only EEPROM

High performance MNOS technology for a byte-erasable, 5-V, 64-kbit EEPROM has been developed with a minimum feature size of 2 microns; this, together with scaling theory implementation for the MNOS device, leads to a cell size of only 180 sq microns, a programming voltage of only 16 V, and a high packing density. The high voltage structure of the MNOS device, as well as the high voltage circuit technology, have been developed to eliminate both DC programming current in the memory array and the high voltage switching circuits for on-chip-generated programming voltage. Byte erasing reliability is obtained by designing the high voltage switching circuits and their control logic in a way that eliminates erroneous writing or erasing due to timing skew.