Group parity prediction scheme for concurrent testing of linear feedback shift registers
Abstract
A group parity prediction scheme which can be used for concurrent testing of linear feedback shift register circuits (LFSRs) is described. The parity of a group of bits (m) in the LFSR at each clock cycle is computed, and the results are compared with the known parity of a four-stage LFSR. Concurrent testing is recommended for the following LFSR applications: the implementation of cyclic redundancy codes; logic testing with serial and parallel signature analyzers; and store address generation.
- Publication:
-
Electronics Letters
- Pub Date:
- January 1985
- DOI:
- 10.1049/el:19850046
- Bibcode:
- 1985ElL....21...67V
- Keywords:
-
- Computer Components;
- Feedback Control;
- Parity;
- Prediction Analysis Techniques;
- Shift Registers;
- Redundancy Encoding;
- Electronics and Electrical Engineering