Nonvolatile, electrically erasable programmable ROM
Abstract
The processing technology for integration of MNOS-EEPROMs and NMOS Logic was investigated as p-well isolation. Memory characteristics of both Si gate and metal gate MNOS devices are investigated for nitride constitution which aims for lower programming voltages and good memory performance. The complete fabrication process for 128 byte SNOS-EEPROM chip is described by using high voltage depletion MOS devices in p-well technology. Another test vehicle uses 4 x 4 metal gate MNOS array to demonstrate possible fabrication of 12 V programmable scaled MNOS devices with 10 years retention after 10 to the 5th power endurance.
- Publication:
-
Final Report
- Pub Date:
- January 1984
- Bibcode:
- 1984vrhp.rept.....E
- Keywords:
-
- Chips (Memory Devices);
- Computer Programs;
- Data Integration;
- Logic Design;
- Metal-Nitride-Oxide-Semiconductors;
- Data Processing;
- Memory (Computers);
- Solid-State Physics