Concurrent simulation techniques exploiting hierarchy

Current fault simulation techniques such as concurrent, deductive, and parallel fault simulation are not powerful enough for today's very large integrated circuit designs. More powerful fault simulation techniques are needed to prevent a crisis in integrated circuit testing. A new simulation technique based on the well-known concurrent and deductive techniques is presented, which uses a hierarchical representation of the circuit design and unlike the traditional implementations of these techniques does not expand the circuit to a single, lowest level, description. The simulation technique is shown to be decoupled from the fault model of the circuit through the use of fault libraries. These libraries are based on the principle that any detectable fault will cause an erroneous output value from some input vector. The implementation of this technique is described and preliminary performance results are given. The advantages and disadvantages of this technique are discussed and possible enhancements are described.