A single chip VLSI architecture for radar signal processing

The problem of how much radar signal processing one can achieve with a single chip signal processor is investigated through the design of a processor architecture suitable for single chip implementation using very large scale integration (VLSI) technology. The design of the single chip processor departs from existing processor designs both in the way it is structured and the manner in which it performs computations. Major emphasis is placed on taking advantage of the parallelism and pipelining inherent in radar signal processing functions, and on novel processor architecture capable of mapping high-level computations (i.e., complex primitives such as Fast Fourier Transform) directly into hardware. The single chip design is based on state-of-the-art technology and utilizes bit-serial arithmetic and externally supplied First-In First-Out memory.