Probabilistic analysis of combinational circuits with random delays
Abstract
System performance is evaluated from the expected values of the output signals. Analytical methods for determining the output expected values of combinational circuits with random delays were developed. The network logic functions, and p.d.f.'s of the delays associated with the gates in the network, it is shown how to obtain the output expected values. Two types of delay elements are considered: the pure delay element, whose output is a delayed, but undistorted, replica of the input and the discriminating delay element, where input rise and fall transitions experience different delays. Two degrees of network complexity are dealt with: treelike networks, in which there is only one path from every network input to any network output and networks with reconvergent fanouts, where more than one path exists from some inputs to some outputs. An approximate model is proposed where the circuits are subdivided into large logic blocks. The analytical techniques previously derived for individual gates are applicable. Various strategies for characterizing the delays of the large logic blocks are considered and examined by computer simulations.
 Publication:

Ph.D. Thesis
 Pub Date:
 January 1984
 Bibcode:
 1984PhDT........13E
 Keywords:

 Delay Circuits;
 Digital Integrators;
 Output;
 Probability Theory;
 Time Lag;
 Computer Networks;
 Computerized Simulation;
 Wave Propagation;
 Electronics and Electrical Engineering