A switch-level model and simulator for MOS digital systems
Abstract
The switch-level model describes the logical behavior of digital systems implemented in metal oxide semiconductor (MOS) technology. In this model a network consists of a set of nodes connected by transistor 'switches', with each node having a state 0, 1, or X (for invalid or uninitialized), and each transistor having a state 'open', 'closed', or 'indeterminate'. Many characteristics of MOS circuits can be modeled accurately, including: ratioed, complementary, and precharged logic; dynamic and static storage; (bidirectional) pass transistors; buses; charge sharing; and sneak paths. In this paper, a formal development of the switch-level model starting from a description of circuit behavior in terms of switch graphs is presented. An algorithm for a logic simulator based on the switch-level model which computes the new state of the network by solving a set of equations in a simple, discrete algebra is described. This algorithm has been implemented in the simulator MOSSIM II and operates at speeds approaching those of conventional logic gate simulators. By developing a formal theory of MOS logic circuits, a greater degree of generality and accuracy than is found in other logic simulators for MOS has been achieved.
- Publication:
-
IEEE Transactions on Computers
- Pub Date:
- February 1984
- Bibcode:
- 1984ITCmp..33..160B
- Keywords:
-
- Computer Programs;
- Digital Systems;
- Mathematical Models;
- Metal Oxide Semiconductors;
- Systems Simulation;
- Very Large Scale Integration;
- Computerized Simulation;
- Gates (Circuits);
- Logic Circuits;
- Network Control;
- Random Access Memory;
- Switching Circuits;
- Electronics and Electrical Engineering