Reliability performance evaluation of an on-board processor for SS-TDMA satellites

A parametric approach is presented for assessing the reliability of the redundancy configurations of SS-TDMA telecommunication satellites. The system is assumed to have a ECL/LSI switching matrix and MOS/LSI for the control unit. The behavior of the system is described in terms of function for the failure rates of the system blocks over a 7 yr mission life. A reliability coefficient of 0.99 over 7 yr is shown to be available using a simple redundancy in both the switching matrix and the control unit, considering a 1000 failure/hr (Fit) rate in the electronic switching circuits. Attention is also given to the effects of the external redundancies on the overall system reliability, particularly with reference to the interconnections between the processor redundancies and the peripheral devices. An overall reliability of 0.9 is found available assuming a 500 Fit rate in the processor, a demodulator failure rate of 3000 Fit, and a modulator Fit rate of 1500. Selection of a three vote majority rule configuration is indicated for the system supervisory functions.