A new method of VLSI conform design for MOS cells
Abstract
An automated method for the design of specialized SSI/LSI-level MOS cells suitable for incorporation in VLSI chips is described. The method uses the symbolic-layout features of the CABBAGE computer program (Hsueh, 1979; De Man et al., 1982), but restricted by a fixed grid system to facilitate compaction procedures. The techniques used are shown to significantly speed the processes of electrical design, layout, design verification, and description for subsequent CAD/CAM application. In the example presented, a 211-transistor, parallel-load, synchronous 4-bit up/down binary counter cell was designed in 9 days, as compared to 30 days for a manually-optimized-layout version and 3 days for a larger, less efficient cell designed by a programmable logic array; the cell areas were 0.36, 0.21, and 0.79 sq mm, respectively. The primary advantage of the method is seen in the extreme ease with which the cell design can be adapted to new parameters or design rules imposed by improvements in technology.
- Publication:
-
Siemens Forschungs und Entwicklungsberichte
- Pub Date:
- 1983
- Bibcode:
- 1983SiFoE..12..225S
- Keywords:
-
- Chips (Electronics);
- Logic Design;
- Metal Oxide Semiconductors;
- Very Large Scale Integration;
- Integrated Circuits;
- Electronics and Electrical Engineering