QPSK switching modulator, phase 2

A breadboard QPSK modulator based on a series connected, dual gate FET switching approach was developed to meet a specification provided by ESA. Direct high level modulation immediatly prior to the downlink output on a satellite repeater avoids amplitude and phase distortions. The characteristics include 8.2 GHz center frequency, 650 MHz 3 dB bandwidth, 0 dB nominal gain, emitter coupled logics, input logic levels, 200 MHz max input data rate and 2 nsec max rise and fall time. It is shown that it is feasible to implement a QPSK modulator with a dual gate FET, but practical limits are a phase error of 2.5 deg (against 2 in specification) and an amplitude imbalance of 0.5 dB over the temperature range. Measurements on single gate FET's indicate that the dual gate FET's could contribute 1.3% phase error due to the device phase change with temperature.