Layout algorithms for the design of very large scale integrated circuits using partitioning
Abstract
Computer aided hierarchical layout of VLSI circuits with building blocks of variable shape and size and with multilayer routing subject to technological and geometrical constraints is described. Basic concepts were developed and algorithms written in FORTRAN and implemented on a PDP-11/60 especially for partitioning into a minimal complete set of cliques; planarization of specific subcircuits like power supply nets; interactive metric placement; strong multilayer routability test; and routing of power supply nets with variable width.
- Publication:
-
NASA STI/Recon Technical Report N
- Pub Date:
- March 1983
- Bibcode:
- 1983STIN...8329620D
- Keywords:
-
- Algorithms;
- Integrated Circuits;
- Large Scale Integration;
- Partitions (Mathematics);
- Computer Aided Design;
- Fortran;
- Layouts;
- Electronics and Electrical Engineering