Multi-valued LSI/VLSI logic design
Abstract
A procedure for synthesizing any large complex logic system, such as LSI and VLSI integrated circuits is described. This scheme uses Multi-Valued Multi-plexers (MVMUX) as the basic building blocks and the tree as the structure of the circuit realization. Simple built-in test circuits included in the network (the main current), provide a thorough functional checking of the network at any time. In brief, four major contributions are made: (1) multi-valued Algorithmic State Machine (ASM) chart for describing an LSI/VLSI behavior; (2) a tree-structured multi-valued multiplexer network which can be obtained directly from an ASM chart; (3) a heuristic tree-structured synthesis method for realizing any combinational logic with minimal or nearly-minimal MVMUX; and (4) a hierarchical design of LSI/VLSI with built-in parallel testing capability.
- Publication:
-
Ph.D. Thesis
- Pub Date:
- 1983
- Bibcode:
- 1983PhDT........60S
- Keywords:
-
- Large Scale Integration;
- Logic Design;
- Very Large Scale Integration;
- Algorithms;
- Electronic Equipment Tests;
- Heuristic Methods;
- Hierarchies;
- Multiplexing;
- Trees (Mathematics);
- Electronics and Electrical Engineering