Inverted transistor gate with FET load
Abstract
The letter outlines preliminary results on a new logic gate for silicon bipolar VLSI. Gate delays below 4 ns have been achieved at 2 microwatt dissipation, demonstrating a power-delay product of only 8 fJ. These results are achieved on a 3 micron minimum feature size oxide isolated process.
- Publication:
-
Electronics Letters
- Pub Date:
- April 1983
- DOI:
- 10.1049/el:19830211
- Bibcode:
- 1983ElL....19..303S
- Keywords:
-
- Field Effect Transistors;
- Gates (Circuits);
- Switching Circuits;
- Transistor Circuits;
- Ttl Integrated Circuits;
- Very Large Scale Integration;
- Heterojunction Devices;
- High Speed;
- Oxide Films;
- Packing Density;
- Response Time (Computers);
- Voltage Regulators;
- Electronics and Electrical Engineering