Serial implementation of Viterbi decoders

This paper describes the implementation of two Viterbi decoders that handle input data serially. Internal computations are also performed in a serial rather than a parallel fashion. This allows for low-cost implementation with moderate complexity, using only standard Schottky TTL and memory chips. Synchronization circuits and input data buffers provide proper operation. Each decoder design was implemented with less than 72 chips. One design is a rate 1/2 decoder with 3-bit input quantization and a path memory length of 64 bits. The other is a rate 2/3 decoder with 4-bit input quantization and a path memory length of 128 bits. Both designs have a constraint length of 7, with an input data rate of 64 kbit/s at the encoder. Bit-error rate (BER) tests indicate a coding gain of 4.5 dB for the rate 1/2 decoder and 3.0 dB for the rate 2/3 decoder at a BER of 0.0001. These findings correspond well with the expected theoretical coding gains with infinite quantization of 4.7 dB and 3.5 dB, respectively.