On testing stuck-open faults in CMOS combinational circuits
Abstract
Recently it has been found that a class of failure related to a particular technology (CMOS) cannot be modelled as the conventional stuck-at fault model. These failures change the combinational behavior of CMOS logic gates into a sequential one. Such a failure is modelled as a fault, called the Stuck-Open fault (SOP). The object of this paper is to develop a procedure to detect single SOPs in combinational circuits. It is shown, that in general, tests generated for stuck-at faults when applied in a particular sequence will detect all single SOP faults. In case of single redundancy in the network, the SOP fault on the redundant line cannot be detected. When there is reconvergent fan-out in the network, there is a one-one correspondence between the conditions for stuck-at fault and stuck-open fault detectability.
- Publication:
-
IN: Annual Allerton Conference on Communication
- Pub Date:
- 1982
- Bibcode:
- 1982ccc..proc..707C
- Keywords:
-
- Cmos;
- Electrical Faults;
- Electronic Equipment Tests;
- Failure Analysis;
- Integrated Circuits;
- Logic Circuits;
- Circuit Reliability;
- Combinatorial Analysis;
- Gates (Circuits);
- Logical Elements;
- Network Analysis;
- Redundant Components;
- Reliability Analysis;
- Test Pattern Generators;
- Electronics and Electrical Engineering