Universal pin electronics
Abstract
A unique and advanced test system architecture which has the ability to put virtually an entire test system into a test head and is capable of operating at repetition rates of 100 MHz and with test vectors of 250,000 bits deep is discussed. In addition, this new architecture has the potential to also provide extended analog capability with greatly improved reliability in a small physical package and at a reduced cost over conventional automatic test equipments. Block diagrams of the overall system, major subsystem and the single channel are presented and described. Specifications of the overall system and the single channel are also presented. In addition to its use as an off-line ATE, this architecture can bring its inherent testing power directly to build-in-test (BIT) applications.
- Publication:
-
NASA STI/Recon Technical Report N
- Pub Date:
- September 1982
- Bibcode:
- 1982STIN...8334196J
- Keywords:
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- Architecture (Computers);
- Circuit Reliability;
- Computer Systems Performance;
- Program Verification (Computers);
- Channels (Data Transmission);
- Test Equipment;
- Electronics and Electrical Engineering